R10000 Microprocessor User's Manual

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4. Cache Organization and Coherency

Each cache is two-way set associative and uses a write back protocol; that is, two cache blocks are assigned to each set (as shown in Figure 4-1), and a cache store writes data into the cache instead of writing it directly to memory. Some time later this data is independently written to memory.

A write-invalidate cache coherency protocol (described later in this chapter) is supported through a set of cache states and external coherency requests.

4.1 - Primary Instruction Cache

4.2 - Primary Data Cache

4.3 - Secondary Cache

4.4 - Cache Algorithms

4.5 - Relationship Between Cached and Uncached Operations

4.6 - Cache Algorithms and Processor Requests

4.7 - Cache Block Ownership